On Packet Scheduling Algorithm for WDM-based Photonic Packet Switch with Fiber Delay Line Buffers

In this paper, we evaluate the performance of the photonic packet switch architecture to which packet scheduling algorithms is applied with fiber delay line buffers which function as the shared buffer. Since, in a shared buffer type switch, a void space introduces unacceptable performance degradation when high traffic load conditions, we propose a void space reduction method to resolve the problem. Our simulation results show that our proposed method achieves the stable performance in the shared buffer type switch under high traffic load conditions. Next, we consider the feasible design of the architecture for the algorithms with a PLD design software, and we discuss the feasibility of the algorithms from the viewpoint of the processing delay time. Through the simulation experiments, we found that the number of wavelengths in the switch greatly influenced the processing delay time.